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File: [Development] / JSOC / proj / tables / img_cnfg_ids
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Revision: 1.1, Thu Sep 26 19:37:11 2013 UTC (9 years, 8 months ago) by prodtest Branch: MAIN CVS Tags: Ver_LATEST, Ver_9-5, Ver_9-41, Ver_9-4, Ver_9-3, Ver_9-2, Ver_9-1, Ver_9-0, Ver_8-8, Ver_8-7, Ver_8-6, Ver_8-5, Ver_8-4, Ver_8-3, Ver_8-2, Ver_8-12, Ver_8-11, Ver_8-10, Ver_8-1, HEAD put in cvs for the first time |
#! Description: Standard Image Configuration Table #Id TapCfg ClearTable ReadTable CropTable LookupTable R N K nrows ncols rowstr colstr datavals datavals_no_overscan 80 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 0 16 UNCOMPRESSED 2 2 2047 2047 16777216 16760836 81 4_PORT fclr_2800_t1.t f4_4096c_t4.t NONE NONE 0 16 UNCOMPRESSED 4 4 2046 2046 16777216 16744464 88 2_PORT_FG fclr_2800_t1.t f2d_4096b_t7.t NONE NONE 0 16 UNCOMPRESSED 2 0 2047 -1 16777216 16769024 89 2_PORT_HE fclr_2800_t1.t f2d_4096b_t7.t NONE NONE 0 16 UNCOMPRESSED 2 0 2047 -1 16777216 16769024 90 4_PORT fclr_2800_t1.t f4_4096emi_t0.t NONE NONE 0 16 UNCOMPRESSED 0 0 -1 -1 16777216 16777216 91 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 0 14 7 2 2 2047 2047 16777216 16760836 92 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 0 14 6 2 2 2047 2047 16777216 16760836 93 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 2 12 5 2 2 2047 2047 16777216 16760836 94 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 2 12 4 2 2 2047 2047 16777216 16760836 95 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 4 10 3 2 2 2047 2047 16777216 16760836 96 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 4 10 2 2 2 2047 2047 16777216 16760836 97 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 0 16 UNCOMPRESSED 2 2 2047 2047 13173808 13157436 98 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE round_14to12.k 0 16 UNCOMPRESSED 2 2 2047 2047 16777216 16760836 99 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r round_14to12.k 0 16 UNCOMPRESSED 2 2 2047 2047 13173808 13157436 100 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r round_14to12.k 0 14 5 2 2 2047 2047 13173808 13157436 101 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r round_14to10.k 0 14 3 2 2 2047 2047 13173808 13157436 102 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 0 14 7 2 2 2047 2047 13173808 13157436 103 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 0 14 6 2 2 2047 2047 13173808 13157436 104 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 2 12 5 2 2 2047 2047 13173808 13157436 105 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 2 12 4 2 2 2047 2047 13173808 13157436 106 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 4 10 3 2 2 2047 2047 13173808 13157436 107 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 4 10 2 2 2 2047 2047 13173808 13157436 108 4_PORT fclr_2800_t1.t f4_4096emi_t0.t NONE NONE 0 14 7 0 0 -1 -1 16777216 16777216 109 4_PORT fclr_2800_t1.t f4_4096emi_t0.t NONE NONE 0 14 6 0 0 -1 -1 16777216 16777216 110 4_PORT fclr_2800_t1.t f4_4096emi_t0.t NONE NONE 2 12 5 0 0 -1 -1 16777216 16777216 111 4_PORT fclr_2800_t1.t f4_4096emi_t0.t NONE NONE 2 12 4 0 0 -1 -1 16777216 16777216 112 4_PORT fclr_2800_t1.t f4_4096emi_t0.t NONE NONE 4 10 3 0 0 -1 -1 16777216 16777216 113 4_PORT fclr_2800_t1.t f4_4096emi_t0.t NONE NONE 4 10 2 0 0 -1 -1 16777216 16777216 114 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE inverse.k 0 16 UNCOMPRESSED 2 2 2047 2047 16777216 16760836 115 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r inverse.k 0 14 6 2 2 2047 2047 13173808 13157436 116 4_PORT fclr_2800_t1.t f4_4096c_t4.t NONE NONE 0 14 7 4 4 2046 2046 16777216 16744464 117 4_PORT fclr_2800_t1.t f4_4096c_t4.t NONE NONE 0 14 6 4 4 2046 2046 16777216 16744464 118 4_PORT fclr_2800_t1.t f4_4096c_t4.t NONE NONE 0 14 5 4 4 2046 2046 16777216 16744464 119 1_PORT_E fclr_6000_t2.t f1_4096a_t5.t NONE NONE 0 16 UNCOMPRESSED 0 0 -1 -1 16777216 16777216 120 1_PORT_F fclr_6000_t2.t f1_4096a_t5.t NONE NONE 0 16 UNCOMPRESSED 0 0 -1 -1 16777216 16777216 121 1_PORT_G fclr_6000_t2.t f1_4096a_t5.t NONE NONE 0 16 UNCOMPRESSED 0 0 -1 -1 16777216 16777216 122 1_PORT_H fclr_6000_t2.t f1_4096a_t5.t NONE NONE 0 16 UNCOMPRESSED 0 0 -1 -1 16777216 16777216 123 2_PORT_EF fclr_6000_t2.t f2s_4096b_t6.t NONE NONE 0 16 UNCOMPRESSED 0 2 -1 2047 16777216 16769024 124 2_PORT_GH fclr_6000_t2.t f2s_4096b_t6.t NONE NONE 0 16 UNCOMPRESSED 0 2 -1 2047 16777216 16769024 160 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 0 14 5 2 2 2047 2047 16777216 16760836 161 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 0 14 4 2 2 2047 2047 16777216 16760836 162 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 1 13 6 2 2 2047 2047 16777216 16760836 163 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 1 13 5 2 2 2047 2047 16777216 16760836 164 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 1 13 4 2 2 2047 2047 16777216 16760836 165 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 1 13 3 2 2 2047 2047 16777216 16760836 166 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 2 12 3 2 2 2047 2047 16777216 16760836 167 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 2 12 2 2 2 2047 2047 16777216 16760836 168 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 3 11 5 2 2 2047 2047 16777216 16760836 169 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 3 11 4 2 2 2047 2047 16777216 16760836 170 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 3 11 3 2 2 2047 2047 16777216 16760836 171 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE NONE 3 11 2 2 2 2047 2047 16777216 16760836 172 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 0 14 5 2 2 2047 2047 13173808 13157436 173 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 0 14 4 2 2 2047 2047 13173808 13157436 175 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 1 13 6 2 2 2047 2047 13173808 13157436 176 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 1 13 5 2 2 2047 2047 13173808 13157436 177 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 1 13 4 2 2 2047 2047 13173808 13157436 178 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 1 13 3 2 2 2047 2047 13173808 13157436 179 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 2 12 3 2 2 2047 2047 13173808 13157436 180 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 2 12 2 2 2 2047 2047 13173808 13157436 181 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 3 11 5 2 2 2047 2047 13173808 13157436 182 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 3 11 4 2 2 2047 2047 13173808 13157436 183 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 3 11 3 2 2 2047 2047 13173808 13157436 184 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r NONE 3 11 2 2 2 2047 2047 13173808 13157436 190 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c4_lut.k 0 14 4 2 2 2047 2047 13173808 13157436 191 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c4_lut.k 0 14 3 2 2 2047 2047 13173808 13157436 192 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c4_lut.k 0 14 2 2 2 2047 2047 13173808 13157436 193 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c5_lut.k 0 14 3 2 2 2047 2047 13173808 13157436 194 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c5_lut.k 0 14 2 2 2 2047 2047 13173808 13157436 195 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c5_lut.k 0 14 1 2 2 2047 2047 13173808 13157436 196 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c3_plin.k 0 14 5 2 2 2047 2047 13173808 13157436 197 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c3_plin.k 0 14 4 2 2 2047 2047 13173808 13157436 198 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c3_plin.k 0 14 3 2 2 2047 2047 13173808 13157436 199 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c3_5_plin.k 0 14 5 2 2 2047 2047 13173808 13157436 200 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c3_5_plin.k 0 14 4 2 2 2047 2047 13173808 13157436 201 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c3_5_plin.k 0 14 3 2 2 2047 2047 13173808 13157436 202 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c4_plin.k 0 14 4 2 2 2047 2047 13173808 13157436 203 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c4_plin.k 0 14 3 2 2 2047 2047 13173808 13157436 204 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c4_plin.k 0 14 2 2 2 2047 2047 13173808 13157436 205 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c4_5_plin.k 0 14 4 2 2 2047 2047 13173808 13157436 206 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c4_5_plin.k 0 14 3 2 2 2047 2047 13173808 13157436 207 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2047.r c4_5_plin.k 0 14 2 2 2 2047 2047 13173808 13157436 208 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE c3_plin.k 0 14 4 2 2 2047 2047 16777216 16760836 209 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE c3_5_plin.k 0 14 4 2 2 2047 2047 16777216 16760836 210 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE c4_plin.k 0 14 3 2 2 2047 2047 16777216 16760836 211 4_PORT fclr_2800_t1.t f4_4096b_t3.t NONE c4_5_plin.k 0 14 3 2 2 2047 2047 16777216 16760836 212 4_PORT fclr_2800_t1.t f4_4096b_t3.t circ2100.r c3_plin.k 0 14 4 2 2 2047 2047 13733200 13716820
| Karen Tian |
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